The present invention relates to precision integrated analog timing circuits.
Analog timing circuits are often used to provide time durations which are too short to be measured by digital timing circuits. One particular area where such circuits are needed is in read-interface circuits which are used to interface to disk drives. (However, this is far from the only application of analog timers.)
In read-interface circuits, the data encoded in the magnetic medium appears electrically (after amplification and possibly some filtering) as a series of pulses. The raw signal includes various rising and falling voltage transitions, but the correct interpretation of this signal (in terms of data bits) requires that the voltage transitions be correctly identified with data bits. Thus reading requires correct phase information. Achieving this phase information requires an accurate timing function. However, the durations involved are too short (e.g. 3-10 nanoseconds) for a digital timing circuit. If the phase information is not correct, the bit error rate will be increased.
The need for an accurate timing function is particularly critical in "PRML" (partial-response-maximum-likelihood) disk-drive read-interface circuits. Such circuits offer significant advantages, but pose the drawback that clock recovery is generally more difficult than in peak detector circuits. See generally, e.g., the following titles, all of which are hereby incorporated by reference: Abidi, "Integrated circuits in magnetic disk drives," ESSCIRC '94 PROCEEDINGS 48 (1994); Roo et al., "Analog timing recovery architectures for PRML detectors," 1 GLOBECOM '95 RECORD 571 (1995); Moore, "A high performance digital read channel for hard disk drives using PRML techniques," CICC '93 Proceedings at pp.10.5.1-10.5.4 (1993); Parsi et al., "A 200 Mb/s PRML read/write channel IC," 1996 ISSCC DIGEST at 66-67 and 419; Tuttle et al., "A 130 Mb/s PRML read/write channel with digital-servo detection," 1996 ISSCC DIGEST at 64-5 and 419; Mita et al., "A 150 Mb/s PRML chip for magnetic disk drives," 1996 ISSCC DIGEST at 62-3 and 418; Pearsen et al., "250 MHz digital FIR filters for PRML disk read channels," 1995 ISSCC DIGEST at 80-1 and 342; Richetta et al., "A 16 MB/s PRML read/write data channel," 1995 ISSCC DIGEST at 78-9 and 342.
Thus precision analog timing circuits must be used. However, the environment of the read interface circuitry (especially in a portable computer) is not friendly: the read interface circuitry must tolerate an ambient temperature range of 0-70.degree. C. Analog circuits are notoriously susceptible to temperature dependence. Temperature variation is particularly inconvenient for analog timing circuits, since such variation may cause the bit error rate to increase, and hence the read operation will be slowed or halted.
Innovative Timing Circuit
The present application discloses a temperature-compensated high-speed timing circuit, which is particularly advantageous in read-interface circuits for disk-drive interface. (However, this circuit can also be used in other analog timer applications.) In this circuit the voltage on the integrating capacitor is compared against a voltage defined by the drop, on a resistor, induced by a current which is the combination of a reference current from a reference current generator with a temperature-dependent current from another current generator.